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VIA EPIA N10000 Nano-ITX Review
Posted on Feb 10, 2006 Go to:

AES Encryption Benchmarking

VIA's AES Benchmark tool is a synthetic AES encryption benchmark for calculating AES encryption speeds through software as well as hardware, although the tool only tests the hardware encryption (AES Core) of the Luke processor. Standard x86 CPUS from AMD and Intel do not have hardware encryption, and perform these calculations in software.

AES Encryption functionality is part of VIA's 'Padlock' Security Suite.

The Advanced Encryption Standard (AES) cipher is used in numerous cryptographic protocols, including TLS (SSL), SSH, and IPSEC. AES is a royalty-free FIPS approved standard intended to ultimately replace DES.

The AES Benchmark Tool is available for download here

We ran 100 iterations for each test, several times over and averaged the results (they can slightly vary each time). Then we converted the results into iterations per minute, to make interpretation easier. Each iteration represents 1000 calculations.

EPIA N - Back Panel Layout

The N10000 can calculate AES instructions directly using the CPU, something our office machines (and most current CPUs) are not able to do. In one minute, we managed 4900 ECB iterations, 2400 CBC and CFB iterations, and 1230 OFB iterations. Our nearest competitor (a 2.4Ghz Pentium IV) managed 368 iterations on its fastest test.

The N10000 was between 4 and 13 times faster than our Pentium IV on each encryption test, an impressive achievement. With software designed to use Padlock technology, the N10000 clearly has a huge advantage over most other boards.

The science bit: The AES core of the Luke CPU performs a single AES block round operation in two processor clock cycles. Pipelined operation is supported for operations on independent blocks, giving a net throughput of one round per clock. ECB mode encryption utilises independent blocks and can be pipelined, whereas CBC, CFB and particularly OFB mode encryption do not - hence the faster encryption times for ECB. Traditional x86 platforms require at least 250 clock cycles per block to perform the same calculations, so even with higher clock speeds they cannot match the C5P's dedicated technology.

More information about how VIA's Padlock works

Video Playback Tests -->

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